STATIC SOFTWARE SCHEMES One bit time stamping

One bit time stamping

Darnell & Kenedy, 1993, Rice University

• Darnell & Kenedy, 1993, Rice University

• Essence: only those cache lines which are not accessed during the epoch changing the shared data - are invalidated

• HW support:

  • Epoch bit is associated with each cache line to notify
    arbitrary access to the cache line during the current epoch
  • HW reset of the epoch bit at each epoch boundary
  • Invalidate instruction simply copies Epoch to Valid bit

• SW support:

  • compile-time (static) insertion of Invalidate instructions
  • insertion is placed et the end of the epoch containing shared data store op.

• Performance - high (very low hit ratio)

• Complexity - low (one additional bit per cache line)