| [ADVE91] | Adve, S.V., Adve, V.S., Hill, M.D., Vernon, M.K., "Comparsion of hardware and software cache coherence schemes," Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, pp. 298-308. |
| [AGARW88] | Agarwal, A., Simoni, R., Hennessy, J., Horowitz, M., "An evaluation of directory schemes for cache coherence," Proceedings of the 15th Annual International Symposium on Computer Architecture, May 1988, pp. 280-289. |
| [ARCHI86] | Archibald, J., Baer, J.-L., "Cache coherence protocols: evaluation using a multiprocessor simulation model," ACM Transactions on Computer Systems, Vol. 4, November 1986, pp. 273-298. |
| [ATKIN87] | Atkinson, R. R., McCreight, E.M., "The Dragon processor," Proceedings of the 2nd International Conference on Architecturak Support for Programming Languages and Operating Systems, 1987, pp. 65-69. |
| [BENN90a] | Bennett, J.K., Carter, J.B., Zwaenepoel, W., "Munin: Distributed shared memory based on type-specific memory coherence," Proceedings of the 1990 Conference on Principles and Practice of Parallel Programming, March 1990, pp. 168-176. |
| [BENN90b] | Bennett, J.K., Carter, J.B., Zwaenepoel, W., "Adaptive software cache management for distributed shared memory architectures," Proceeding of the 17th Annual International Symposium on Computer Architecture, June 1990, pp. 125-134. |
| [BRANT85] | Brantley, W.C., McAuliffe, K.P., Weiss, J., "RP# processor-memory element," Proceedings of the 1985 International Conference on Parallel Processing, August 1985, pp. 782-789. |
| [CENSI78] | Censier, L.M., Feautrier, P., "A new solution to coherence problem in multicache systems," IEEE Transactions on Computers, Vol. C-27, No. 12, December 1978, pp. 1112-1118. |
| [CHERI86] | Cheriton, D.R., Slavenburg, G.A., Boyle, P.D., "Software-controlled caches in the VMP multiprocessor," Proceedings of the 13th Annual International Symposium on Computer Architecture, June 1986, pp. 366-374. |
| [CHEO88a] | Cheong, H., Veidenbaum, A.V., "A cache coherence scheme with fast selective invalidation," Proceedings of the 15th Annual IOnternational Symposium on Computer Architecture, May 1988, pp. 299-307. |
| [CHEO88b] | Cheong, H., Veidenbaum, A.V., "Stale data detection and coherence enforcement using flow analysis," Proceedings of the 1988 International Conference on Parallel Processing, August 1988, pp. 138-145. |
| [CHEON89] | Cheong, H., Veidenbaum, A.V., "A version control approach to cahce coherence," Proceedings of the International Conference on Supercomputing 89, June 1989, pp. 322-330. |
| [CHEON90] | Cheong, H., Veidenbaum, A.V., "Compiler-directed cache management in multiprocessors," IEEE Computer, Vol. 23, No.6, June 1990, pp. 39-47. |
| [CYTRO88] | Cytron, R., Karlovsky,S., McAuliffe, K.P., "Automatic management of programmable caches," Proceedings of the 1988 International Conference on Parallel Processing, 1988, pp. 229-238. |
| [EDLER85] | Edler, J., Gottlieb, A., Kruskal,C.P., McAuliffe, K.P., Rudolph, L., Snir, M., Teller, P., Wilson, J., "Issues related to MIMD shared-memory computers: the NYU Ultracomputers approach," Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985, pp. 126-135. |
| [EGGER89] | Eggers, S.J., Katz, R.H., "Evaluating the performance of four snooping cache coherency protocols," Proceedings of the 16th Annual International Symposium on Computer Architecture, June 1989, pp. 2-15. |
