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Digital Equipment Corporation.

The first product realizing the Alpha AXP architecture is labeled 21064.

The Alpha is a 64-bit RISC-type microprocessor.

IBM, Motorola, and Apple.

The first PowerPC implementation is the PowerPC 601 microprocessor
(also called MPC 601 by Motorola, and PPC 601 by IBM).

Sun Microsystems.

The name SPARC stands for scalable processor architecture.

The SPARC architecture follows the Berkeley RISC design philosophy.

MIPS Computer Systems.

The MIPS acronym stands for microprocessor without interlocked pipeline stages.

The MIPS system originated at Stanford University in the early eighties.

The i860 RISC was first announced in 1989.
It features on-chip FPU, dual cache, and graphics unit
(the first microprocessor with such a feature).

The first members of the M88000 family are the MC88100 and MC88200.
They were followed by the RISC MC88110,
which is a two-issue superscalar.

The PA-RISC architecture was designed to be scaleable
across technologies, cost ranges, performance ranges,
and to provide price-performance advantages.

Legend: * 64-bit microprocessors, all others are 32-bit microprocessors.

x L—x-layer metal (x = 2, 3, 4);
PGA—pin grid array;

BGA—ball grid array;

LGA—land grid array;

SEC—single edge contact;

IU—integer unit;
FPU—floating point unit;
VA—virtual address [bits];
PA—physical address [bits];

EC Dbus—external cache data bus width [bits];

SYS Dbus—system bus width [bits];
RB—rename buffer [size expressed in the number of registers];

* Can also be used as a 16´ 64 register file.

ILP = instruction level parallelism;

LSU = load/store or address calculation unit;
IU = integer unit;
FPU = floating point unit;
GU = graphics unit;

* Superpipelined;

** RISC instructions, one or more of them are needed to emulate an 80x86 instruction;

*** MMX (multimedia extensions) unit.

Icache—on-chip instruction cache;

Dcache—on-chip data cache;
L2 cache—on chip L2 cache;

DIR—direct mapped;
xWSA—x-way set associative;

UNI—unified L1 instruction and data cache;
* on-chip cache controller for external L2 cache;

** on-chip cache controller for external L1 cache;

*** L2 cache is in the same package, but on a different silicon die.

ITLB—translation lookaside buffer for code [entries];
DTLB—translation lookaside buffer for data [entries];
2WSA—two-way set associative; ASOC = fully associative;
UNI—unified TLB for code and data;

BPS—branch prediction strategy;

2BC—two-bit counter;

3BSR—three bit shift register;
RAS—return address stack;
ICS—instruction cache size (2BC for every instruction in the instruction cache);

* hinted instructions available for static branch prediction.

Figure MPSS1: Pentium pin layout (source: [Intel93])

Legend: Self-explanatory.

• 100% binary compatible with ancestors.
• Enhancements and additions to i486:
• Superscalar Architecture
• Dynamic Branch Prediction
• Pipelined Floating-Point Unit
• Improved Instruction Execution Time
• Separate 8K Code and Data Caches
• Writeback MESI Protocol (Data Caches)
• 64-Bit Data Bus
• Bus Cycle Pipelining
• Address Parity
• Internal Parity Checking
• Functional Redundancy Checking
• Execution Tracking
• Performance Monitoring
• IEEE 1149.1 Boundary Scan
• System Management Mode
• Virtual Mode Extensions
• New instructions
  to accommodate the additional functionality.
• The MMU fully compatible with i386 and i486.
• The floating-point unit completely redesigned,
  compared with i486.

Figure MPSS2: Pentium pin functions (source: [Intel93])

Legend:

TAP—Processor boundary scan.

Figure MPSS3: Pentium block digaram (source: [Intel93])

Legend:

TLB—Translation Lookaside Buffer.

Figure MPSS4: Intel 486 pipeline versus Pentium pipeline (source: [Intel93])

Legend:

PF—Prefetch;

D1/2—Decoding 1/2;

EX—Execution;

WB—Writeback.

• In the PF stage,
  two independent prefetch buffers
  and the branch target buffer
  operate in conjunction.
• One prefetch buffer requests prefetches
  at any given time.
• Prefetches are requested sequentially,

• Two parallel decoders attempt to decode and issue
  the next two sequential instructions.
• The decoders determine whether one or two instructions can be issued, based on the instructions pairing rules.
• If prefixes, an extra D1 clock is needed.
• Prefixes go only to the u-pipeline,

• The addresses of memory resident operands
  are calculated.
• One clock cycle for both address calculations,
  in displacement + immediate data instructions,
  and base + index addressing instructions
  (i486 requires two cycles).

• Used for both, ALU operations and data cache access.
• Two clocks if both present,
  ALU operation + data cache access.
• All u-pipe instructions,
  and all v-pipe instructions except conditional branches,
  verified for correct branch prediction.

• Instructions enabled to modify processor state,
  and to complete the execution.
• The v-pipe conditional branches
  verified for correct branch prediction.

• Conditions for pairing:

• BTB used to predict
  the outcome of branch instructions.
• Current address in D1 is applied to BTB.
• If hit,
  the assumption is that the branch will be taken
  (if the assumption is correct,
  execution goes without stalls and flushes).
• If miss,
  the assumption is the branch will not be taken.
• A mispredicted branch
  (weather BTB hit or miss)
  causes the pipeline to be flushed.
• The number of delay clocks
  depends on the branch type.
• Write Buffers + Memory Ordering:

• Two write buffers (one per pipe)
  to enhance the performance of
  consecutive writes to memory.
• Can be filled in one clock,

• Loop for computing prime numbers:

• When the system changes the value of
  NMI, INTR, FLUSH#, SMI#, or INIT,
  as the result of executing an OUT instruction,
  these inputs must be at a valid state
  three clocks before BRDY# is returned,
  to ensure that the new value is recognized,
  before the next instruction is executed.
• An OUT instruction can be used
  to modify AZOM#.

• After executing certain instructions,
  the Pentium processor serializes instruction execution.
• This means that any modifications
  to flags, registers, and memory,
  for previous instructions are completed,
  before the next instruction is fetched and executed.
• The prefetch queue is flushed
  as a result of the serializing operations.
• The Pentium processor serializes
  the instruction execution
  after executing one of the instructions:
  MSR (Move to Special Register),
  INVD, INVLPG, IRET, IRETD, CPUID, ...

• Pentium recognizes 7 external interrupts
  with the following priority:

• In addition to two write buffers,
  Pentium processor has three writeback buffers
  (1-line-deep and 32-bytes-wide).
• First:
  A dedicated replacement writeback buffer,
  which causes writebacks due to linefill
  that replaces a modified line in the data cache.
• Second:
  One external snoop writeback buffer,
  to store writeback caused by an inquire cycle
  that hits a modified line in the data cache.
• Third:
  One internal snoop writeback buffer,
  to store writebacks
  caused by a modified line in the data cache.

• Model specific registers (MSRs) are used in
  execution tracing, performance monitoring, testing,
  and machine check errors.
• Two new instructions are used
  to access these registers:

Figure MPSS5: Model specific register manipulation (source: [Intel93])

Legend:

H—Hexadecimal.

• On the same chip with the CPU.
• Heavily pipelined.
• One floating-point instruction (FPI)
  in every clock cycle.
• It can receive up to two FPIs,
  one of which must be an exchange instruction.

• The Pentium FPU has 8 pipeline stages;
  the first 5 are shared with the integer unit.
• The floating-point pipeline stages are:

• One 8-KB data cache and
  one 8-KB code cache.
• The data cache fully supports the MESI
  writeback cache consistency protocol:
  MESI = modified/exclusive/shared/invalid.
• The data cache is configurable as write-back
  or write-through,
  on a line by line basis.
• Parts of data memory
  can be defined as non cacheable,
  by software or external hardware.
• The code cache is inherently write protected,
  and supports a subset of MESI called SI.

• Each cache is 2-way set associative,
  with 128 sets in each cache,
  each set containing two 32-bytes wide lines.
• Both caches use the LRU replacement,
  which requires one bit per set,
  in each one of the caches.
• Data cache includes two state bits to support MESI.
• Code cache includes one state bit to support SI.
• The operating modes of the caches are controlled
  by the CD (code disable)
  and NW (not write through) bits in CR0.
• For best performance:

Figure MPSS6: Organization of instruction and data caches (source: [Intel93])

Legend:

MESI—Modified/Exclusive/Shared/Invalid;

LRU—Least Recently Used.

Figure MPSS7: Generation of PCD and PWT (source: [Intel93])

Legend:

PCD—a bit which controls cacheability on a page by page basis;

PWT—a bit which controls write policy for the second level caches;

PTRS—Pointers.

• Two bits for cache control (PWT and PCD)
  are defined in the page table
  and page directory entries.
• The states of these bits are driven out
  on the PWT and PCD pins
  during memory access cycles.
• The PWT bit controls write policy
  for the second level caches:

• Inquire cycles are initiated by the system
  to determine if a line is present
  in the code or data cache,
  and what its state is
  (term "snoop cycle" has the same meaning).
• If the inquired (snooped) line is in data cache,
  and in the "modified" state,
  processor has the most recent information,
  and must schedule a writeback.

• The on-chip caches can be flushed
  by external hardware or internal software.
• Flushing by hardware:
  driving the FLUSH# pin low.
• Flushing by software:
  The INVD and WBINVD instructions
  cause on-chip caches to be invalidated.

• Every line in the Pentium processor data cache
  is assigned a state.
• This is a set of rules
  by which states are assigned to cache entries (lines),
  based on Pentium activities,
  and the activities of other bus masters.
• The states define whether a line is valid
  (hit or miss),
  whether it is available to other caches
  (exclusive or shared),
  and whether it has been modified
  (modified or not).

Figure MPSS8: Definition of states for the MESI and the SI protocols (source: [Intel93])

Legend:

LINE FILL—Fetching the whole line into the cache from main memory.

Legend:

*—Locked accesses to the data cache will cause the accessed line to transition to the Invalid state.

Legend:

WB/WT—Writeback/Writethrough.

Figure MPSS11: Data cache state transitions during inquire cycles (source: [Intel93])

Legend:

INV—Invalid bit.

[Intel93] "Pentium Processor User’s Manual," Intel, Santa Clara California, USA, 1993.

vm@etf.rs

MMX—MultiMedia eXtension.

• Birthday: Nov 1, 1995 (10 months after 1^st silicon)
• Technology:
  BiCMOS 0.6m m (0.3m m) 150MHz (200MHz) 5.5MTr
• Performance:
  6.1 (8.1) SPECint95 + 5.5 (6.8) SPECfp95
• Processor: 32 bits (40 registers) BTB
  Bus: 64 bits (internal and external) 50 MHz (66 MHz)
• Split transactions: Decoupled address/data cycles
• Superpipelined: 14 stages
• Superscalar (SHT)
  IFU fetches 16 bytes per clock cycle;
  IDU decodes 3 instructions per clock cycle
• Speculative and out-of-order execution
• On-chip L1 cache: 8KB (inst) + 8KB (data) 2wSA
  + buffers for 4 outstanding misses
• On-package L2 cache: 256 KB (dual-cavity PGA) 4wSA + 8ECC bits per 64 data bits
• Support for SMP/DSM:
  MESI + dedicated ports (1 In + 1 Out)
• Dedicated I/O ports: 1 In + 1 Out (MCS + DCS)

Legend:

SB—single independent bus;

DIB—dual independent bus;

CLC—control logic chipset;

L2—second level cache.

• 1000M transistors per chip
• <40 Å gate oxide thickness
• <0.10 m m minimum lithographic dimension
• 4000 MHz
• 100 BIPS

• Microprocessor’s performance trend:
  2´ every 18 months Þ performance at year 2001
  should reach 100 SPECint95 (3500 SPECint92)
• How to design future microprocessors
  so as to maintain the performance trend?

Figure MPSS1: Microprocessor chip delay trends (source: [Sheaffer96])

Metal 2 (2 mm)—Two level metal.

Legend:

est—estimated.

Figure MPSS3: Microprocessor chip operation frequency (source: [Sheaffer96])

PP—Pentium Processor;

PPro—Pentium Pro Processor.

Figure MPSS4: Microprocessor and memory complexity (source: [Sheaffer96])

L1/2—First/second level cache.

vm@etf.rs